1. Field of the Invention
This invention relates to a semiconductor storage device, having a test function which shortens wafer tests.
Priority is claimed on Japanese Patent Application No. 2008-020779, filed Jan. 31, 2008, the content of which is incorporated herein by reference.
2. Description of Related Art
When manufacturing semiconductor storage devices, in order to perform processes efficiently when sealing chips into packages, defective chips are not processed. For this reason, characteristic and operation tests are performed in the wafer state insofar as possible to detect defective chips.
When performing tests in the wafer state, a plurality of probes (contact needles) provided on the probe card of a tester (semiconductor testing device) are brought into contact with the bonding pads of each chip. The tester exchanges control signals (signals controlling data writing and reading), data, and other signals with the chip, and by this means executes tests to judge whether each chip is defective or not.
A tester as described above includes numerous interfaces to perform input and output of the above described signals with a semiconductor storage device and driver circuits to output the various signals.
As semiconductor devices acquire more sophisticated functions, the number of chips on a wafer, and the number of input/output terminals (hereafter “I/O terminals”) on each chip, increase. For this reason, when testing semiconductor devices formed on a wafer, limits are imposed on the number of interfaces to perform signal input/output and on the number of driver circuits to output the signals. As a result, testing of chips on a wafer must be performed in a plurality of sessions, and long lengths of time have been required for tests and inspections of semiconductor devices.
In order to shorten the time required for inspections, Japanese Unexamined Patent Application, First Publication No. 2003-151299 discloses the general semiconductor storage device shown in FIG. 8. There is a method in which, when the data input circuit and data output circuit in this semiconductor storage device have the structures shown in FIG. 9 and FIG. 10 respectively, probes are brought into contact with the bonding pads as explained below, and tests are performed.
A DQ shift test mode function is provided which, when for example there are 32 input/output data terminals, employs DQS (data strobe signals) to cause data output while shifting at every four I/O terminals and perform data writing and reading, in order to manage with a small number of pins to reduce the number of interface circuits and driver circuits.
Hence the probe card of the wafer tester has eight I/O pins connected in common, and probes must be contacted with the bonding pads of all the I/O terminals. Hence there is the problem that during design of the probe card, the number of probes is limited.
However, it is conceivable that, in response to the problem of the occurrence of limitations on the number of probes due to increases in the number of I/O terminals and the number of chips, when testing semiconductor storage devices having a plurality of output terminals, such as for example 32 input/output terminals corresponding to data input/output, tests may be performed by performing data input/output tests for a small number of four pins.
As a result, the probes of the probe card can be used efficiently, testing of numerous chips on the wafer can be performed, and the wafer test TAT (turn-around time) can be shortened.
On the other hand, when only four I/O terminals are selected and probes are contacted to perform tests, when there are 32 I/O terminals, tests of the remaining 28 I/O terminals are not performed, and so quality assurance of all the I/O terminals is not possible.
Hence by adopting a configuration in which a plurality of I/O terminals are consolidated into one block, and at the time of writing data are input to one among the I/O terminals comprised by the block, data are caused to be input to all I/O terminals for the block, and the number of probes can be greatly reduced (see for example Japanese Unexamined Patent Application, First Publication No. 2003-151299).
That is, in the case of the above configuration, when in the above-described DQ shift test mode, and when writing data as shown in the timing chart of FIG. 11, write operations to all I/O terminals are performed simultaneously, so that processing can be performed similarly to that of normal operation.
However, as shown in the timing chart of FIG. 12, when performing data reading the test mode signals TDQj to TDQj+7, which control activation and deactivation of the FIFO (First-In, First-Out) circuits for each of the I/O terminals, are respectively input.
Here, in FIG. 11, the same data are input to all of the bonding pads DQj to DQj+7. FIG. 11, the data WBSRj to WBSRj+7 on the clock rising side are all the same data, and the data WBSFj to WBSFj+7 on the clock falling side are all the same data. In FIG. 11 and FIG. 12, the timing chart for the other bonding pads DQj+8 to DQj+15, DQj+16 to DQj+23, DQj+24 to DQj+31, and for the bonding pads DQSi+1 to DQSi+3, are omitted, but are similar to the timing charts for the bonding pads DQj to DQj+7 and for the bonding pad DQSi.
By means of these test mode signals, one among the eight FIFO circuits connected in common to a single probe is activated and the others deactivated, so that there is no contention and collision of read-out data, and data read processing is performed in order for memory corresponding to each of the I/O terminals.
Hence during writing in the semiconductor device disclosed in Japanese Unexamined Patent Application, First Publication No. 2003-151299, write operation is performed by means of processing similar to that of normal operations, as described above, and so a special circuit is not needed. On the other hand, during reading, the result of comparing and combining the data corresponding to I/O terminals in each block is output, so that there is the problem that it is not possible to judge whether data corresponding to any of the I/O terminals is defective.
Further, this semiconductor device is configured such that the data resulting from combination of data in each block are output from one of the I/O terminals within the block. Consequently a circuit to switch the I/O terminal between normal operation and test mode is necessary. As a result, there is the drawback that differences in the delay times of data output in normal operation occur among the I/O terminals.